Cache and Interconnect Architectures in Multiprocessors by Patricia J. Teller (auth.), Michel Dubois, Shreekant S.

By Patricia J. Teller (auth.), Michel Dubois, Shreekant S. Thakkar (eds.)

Cache And Interconnect Architectures In Multiprocessors Eilat, Israel might 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems the purpose of the workshop used to be to compile researchers engaged on cache coherence protocols for shared-memory multiprocessors with numerous interconnect architectures. Shared-memory multiprocessors became practicable structures for lots of purposes. Bus­ dependent shared-memory structures (Eg. Sequent's Symmetry, Encore's Multimax) are at present constrained to 32 processors. the 1st aim of the workshop was once to profit concerning the functionality ofapplications on present cache-based platforms. the second one aim was once to benefit approximately new community architectures and protocols for destiny scalable platforms. those protocols and interconnects may enable shared-memory architectures to scale past present imitations. The workshop had 20 audio system who observed their present study. The discussions have been vigorous and cordial sufficient to maintain the members clear of the fantastic sand and sunlight for 2 days. The individuals received to understand one another good and have been capable of proportion their techniques in an off-the-cuff demeanour. The workshop was once equipped into numerous periods. The precis of every consultation is defined under. This publication offers revisions of a few of the papers offered on the workshop.

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Put differently, MP trace-driven simulation generally cannot represent interacting processes correctly: the interactions represented by MP tracedriven simulation generally do not correspond to correct execution of the algorithm in the hypothetical architecture. The basic reasons for this are easy to see: interacting processes are dynamic - their intertrace concurrency relationships and their actions generally change during the interactions based on the results of the ongoing interactions. However, trace-driven simulation is generally unable to change the intertrace concurrency relationships and/or trace content to represent these dynamic dependencies correctly.

This solution is adopted in the Sun 3/200 line of workstations [10] and the Apollo DN4000 workstation [4]. In a set-associative cache, virtual addresses which are synonyms could be allocated such that they select the same cache set, Le. they are modulo the ratio of the cache size and of the set size. In this case, they all map to the same cache set and the snooping cache consistency protocol can always detect information sharing. All bus transactions must pass with the physical address the bits of the virtual address selecting the set inside the superset.

Moreover, with the above organization, the occupancy ratio of the cache in some cases is less than 100% and this under-utilization affects the hit ratio. 2 Critical Associativity The deleterious effect on the occupancy ratio can be eliminated provided the degree of associativity of at least one of the two directories is equal to or greater than the critical associativity. For a given cache size the critical associativity is defined as: [Cache Size] / [Page Size]. In this case, the set selection is done only with bits belonging to the page displacement and all blocks that are synonyms map in the same set.

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